mc74vhc157 quad 2-channel multiplexer the mc74vhc157 is an advanced highspeed cmos quad 2channel multiplexer, fabricated with silicon gate cmos technology. it achieves highspeed operation similar to equivalent bipolarschottky ttl, while maintaining cmos lowpower dissipation. it consists of four 2input digital multiplexers with common select (s) and enable (e ) inputs. when e is held high, selection of data is inhibited and all the outputs go low. the select decoding determines whether the a or b inputs get routed to the corresponding y outputs. the internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output. the inputs tolerate voltages up to 7 v, allowing the interface of 5 v systems to 3 v systems. ? high speed: t pd = 4.1 ns (typ) at v cc = 5 v ? low power dissipation: i cc = 4 a (max) at t a = 25 c ? high noise immunity: v nih = v nil = 28% v cc ? power down protection provided on inputs ? balanced propagation delays ? designed for 2 v to 5.5 v operating range ? low noise: v olp = 0.8 v (max) ? pin and function compatible with other standard logic families ? latchup performance exceeds 300 ma ? esd performance: hbm > 2000 v; machine model > 200 v ? chip complexity: 82 fets figure 1. pin assignment 13 14 15 16 9 10 11 12 5 4 3 2 1 8 7 6 s y0 b0 a0 y1 b1 a1 gnd y3 b3 a3 e v cc b2 a2 y2 ? semiconductor components industries, llc, 2001 may, 2001 rev. 4 1 publication order number: mc74vhc157/d soic eiaj16 ordering information mc74vhc157m soic eiaj16 50 units/rail http://onsemi.com device package shipping mc74vhc157d soic16 48 units/rail mc74vhc157dr2 soic16 2500 units/reel soic16 d suffix case 751b tssop16 dt suffix case 948f soic eiaj16 m suffix case 966 marking diagrams 1 8 9 16 1 8 16 9 1 16 9 8 vhc157 awlyyww a = assembly location l, wl = wafer lot y, yy = year w, ww = work week vhc 157 alyw 74vhc157 alyw mc74vhc157dt tssop16 96 units/rail mc74vhc157mel 2000 units/reel mc74vhc157dtr2 tssop16 2500 units/reel
mc74vhc157 http://onsemi.com 2 figure 2. expanded logic diagram 4 7 9 12 2 3 5 6 11 10 14 13 15 1 a0 b0 a1 b1 a2 b2 a3 b3 y0 y1 y2 y3 e s data outputs nibble inputs function table e s y0 y3 a0 a3, b0 b3 = the levels of the respective dataword inputs. h l l x l h l a0a3 b0b3 inputs outputs 3 e s a0 b0 a1 b1 a2 b2 2 5 6 11 10 14 13 12 9 7 4 y0 mux y1 y2 y3 en 1 15 a3 b3 g1 1 1 figure 3. iec logic symbol
mc74vhc157 http://onsemi.com 3 maximum ratings (note 1) symbol parameter value unit v cc dc supply voltage 0.5 to 7.0 v v i dc input voltage 0.5 to v cc 7.0 v v o dc output voltage 0.5 to v cc 7.0 v i ik dc input diode current v i gnd 20 ma i ok dc output diode current v o gnd 20 ma i o dc output sink current 25 ma i cc dc supply current per supply pin 100 ma t stg storage temperature range 65 to 150 c t l lead temperature, 1 mm from case for 10 seconds 260 c t j junction temperature under bias 150 c ja thermal resistance 250 c/w p d power dissipation in still air at 85 c 250 mw msl moisture sensitivity level 1 f r flammability rating oxygen index: 30% 35% ul94vo (0.125 in) v esd esd withstand voltage human body model (note 2) machine model (note 3) charged device model (note 4) >2000 >200 n/a v i latchup latchup performance above v cc and below gnd at 85 c (note 5) 500 ma 1. absolute maximum continuous ratings are those values beyond which damage to the device may occur. extended exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. functional operation under absolute maximumrated conditions is not implied. 2. tested to eia/jesd22a114a. 3. tested to eia/jesd22a115a. 4. tested to jesd22c101a. 5. tested to eia/jesd78. recommended operating conditions symbol characteristics min max unit v cc dc supply voltage 2.0 5.5 v v in dc input voltage (note 6) 0 5.5 v v out dc output voltage 0 v cc v t a operating temperature range, all package types 55 125 c t r , t f input rise or fall time v cc = 3.3 v 0.3 v v cc = 5.0 v 0.5 v 0 0 100 20 ns/v 6. unused inputs may not be left open. all inputs must be tied to a highlogic voltage level or a lowlogic input voltage level. device junction temperature versus time to 0.1% bond failures junction temperature c time, hours time, years 80 1,032,200 117.8 90 419,300 47.9 100 178,700 20.4 110 79,600 9.4 120 37,000 4.2 130 17,800 2.0 140 8,900 1.0 1 1 10 100 1000 failure rate of plastic = ceramic until intermetallics occur figure 4. failure rate vs. time junction temperature normalized failure rate time, years t j = 130 c t j = 120 c t j = 110 c t j = 100 c t j = 90 c t j = 80 c
mc74vhc157 http://onsemi.com 4 dc characteristics (voltages referenced to gnd) v cc t a = 25 c t a 85 c 55 c t a 125 c symbol parameter condition (v) min typ max min max min max unit v ih highlevel input voltage 2.0 3.0 to 5.5 1.5 0.7 v cc 1.5 0.7 v cc 1.5 0.7 v cc v v il lowlevel input voltage 2.0 3.0 to 5.5 0.5 0.3 v cc 0.5 0.3 v cc 0.5 0.3 v cc v v oh highlevel output voltage v in = v ih or v il i oh = 50 a 2.0 3.0 4.5 1.9 2.9 4.4 2.0 3.0 4.5 1.9 2.9 4.4 1.9 2.9 4.4 v v in = v ih or v il i oh = 4 ma i oh = 8 ma 3.0 4.5 2.58 3.94 2.48 3.8 2.34 3.66 v ol lowlevel output voltage v in = v ih or v il i ol = 50 a 2.0 3.0 4.5 0.0 0.0 0.0 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 v v in = v ih or v il i oh = 4 ma i oh = 8 ma 3.0 4.5 0.36 0.36 0.44 0.44 0.52 0.52 i in input leakage current v in = 5.5 v or gnd 0 to 5.5 0.1 1.0 1.0 a i cc quiescent supply current v in = v cc or gnd 5.5 4.0 40.0 40.0 a ????????????????????????????????? ????????????????????????????????? ac electrical characteristics (input t r = t f = 3.0 ns) t a = 25 c t a 85 c 55 c t a 125 c symbol characteristic test conditions min typ max typ max typ max unit ???? ? ?? ? ???? t plh , t phl ?????? ? ???? ? ?????? propagation delay, a to b to y ????????? ? ??????? ? ????????? v cc = 3.3 0.3 v c l = 15 pf c l = 50 pf ??? ? ? ? ??? ??? ? ? ? ??? 6.2 8.7 ??? ? ? ? ??? 9.7 13.2 ?? ?? ?? 1.0 1.0 ??? ? ? ? ??? 11.5 15.0 ???? ? ?? ? ???? 1.0 1.0 ???? ? ?? ? ???? 11.5 15.0 ?? ?? ?? ns ???? ???? ?????? ?????? ????????? ????????? v cc = 5.0 0.5 v c l = 15 pf c l = 50 pf ??? ??? ??? ??? 4.1 5.6 ??? ??? 6.4 8.4 ?? ?? 1.0 1.0 ??? ??? 7.5 9.5 ???? ???? 1.0 1.0 ???? ???? 7.5 9.5 ?? ?? ???? ? ?? ? ???? t plh , t phl ?????? ? ???? ? ?????? propagation delay, s to y ????????? ? ??????? ? ????????? v cc = 3.3 0.3 v c l = 15 pf c l = 50 pf ??? ? ? ? ??? ??? ? ? ? ??? 8.4 10.9 ??? ? ? ? ??? 13.2 16.7 ?? ?? ?? 1.0 1.0 ??? ? ? ? ??? 15.5 19.0 ???? ? ?? ? ???? 1.0 1.0 ???? ? ?? ? ???? 15.5 19.0 ?? ?? ?? ns ???? ? ?? ? ???? ?????? ? ???? ? ?????? ????????? ? ??????? ? ????????? v cc = 5.0 0.5 v c l = 15 pf c l = 50 pf ??? ? ? ? ??? ??? ? ? ? ??? 5.3 6.8 ??? ? ? ? ??? 8.1 10.1 ?? ?? ?? 1.0 1.0 ??? ? ? ? ??? 9.5 11.5 ???? ? ?? ? ???? 1.0 1.0 ???? ? ?? ? ???? 9.5 11.5 ?? ?? ?? ???? ???? t plh , t phl ?????? ?????? propagation delay, e to y ????????? ????????? v cc = 3.3 0.3 v c l = 15 pf c l = 50 pf ??? ??? ??? ??? 8.7 11.2 ??? ??? 13.6 17.1 ?? ?? 1.0 1.0 ??? ??? 16.0 19.5 ???? ???? 1.0 1.0 ???? ???? 16.0 19.5 ?? ?? ns ???? ? ?? ? ???? ?????? ? ???? ? ?????? ????????? ? ??????? ? ????????? v cc = 5.0 0.5 v c l = 15 pf c l = 50 pf ??? ? ? ? ??? ??? ? ? ? ??? 5.6 7.1 ??? ? ? ? ??? 8.6 10.6 ?? ?? ?? 1.0 1.0 ??? ? ? ? ??? 10.0 12.0 ???? ? ?? ? ???? 1.0 1.0 ???? ? ?? ? ???? 10.0 12.0 ?? ?? ?? ???? ???? c in ?????? ?????? input capacitance ????????? ????????? ??? ??? ??? ??? 4 ??? ??? 10 ?? ?? ??? ??? 10 ???? ???? ???? ???? 10 ?? ?? pf typical @ 25 c, v cc = 5.0 v c pd power dissipation capacitance (note 7) 20 pf 7. c pd is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption with out load. average operating current can be obtained by the equation: i cc(opr ) = c pd v cc f in + i cc . c pd is used to determine the noload dynamic power consumption: p d = c pd v cc 2 f in + i cc v cc .
mc74vhc157 http://onsemi.com 5 noise characteristics (input t r = t f = 3.0 ns; c l = 50 pf; v cc = 5.0 v) t a = 25 c symbol characteristic typ max unit v olp quiet output maximum dynamic v ol 0.3 0.8 v v olv quiet output minimum dynamic v ol 0.3 0.8 v v ihd minimum high level dynamic input voltage 3.5 v v ild maximum low level dynamic input voltage 1.5 v a, b, or s figure 5. switching waveform e v cc gnd 50% 50% v cc figure 6. inverting switching y *includes all probe and jig capacitance. c l * test point device under test output figure 7. test circuit v cc gnd y t phl t plh 50% 50% v cc input figure 8. input equivalent circuit t phl t plh
mc74vhc157 http://onsemi.com 6 package dimensions soic16 d suffix case 751b05 issue j notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 18 16 9 seating plane f j m r x 45 g 8 pl p b a m 0.25 (0.010) b s t d k c 16 pl s b m 0.25 (0.010) a s t dim min max min max inches millimeters a 9.80 10.00 0.386 0.393 b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.054 0.068 d 0.35 0.49 0.014 0.019 f 0.40 1.25 0.016 0.049 g 1.27 bsc 0.050 bsc j 0.19 0.25 0.008 0.009 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 5.80 6.20 0.229 0.244 r 0.25 0.50 0.010 0.019 tssop dt suffix case 948f01 issue o ??? ??? dim min max min max inches millimeters a 4.90 5.10 0.193 0.200 b 4.30 4.50 0.169 0.177 c --- 1.20 --- 0.047 d 0.05 0.15 0.002 0.006 f 0.50 0.75 0.020 0.030 g 0.65 bsc 0.026 bsc h 0.18 0.28 0.007 0.011 j 0.09 0.20 0.004 0.008 j1 0.09 0.16 0.004 0.006 k 0.19 0.30 0.007 0.012 k1 0.19 0.25 0.007 0.010 l 6.40 bsc 0.252 bsc m 0 8 0 8 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a does not include mold flash. protrusions or gate burrs. mold flash or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 (0.010) per side. 5. dimension k does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the k dimension at maximum material condition. 6. terminal numbers are shown for reference only. 7. dimension a and b are to be determined at datum plane -w-. section nn seating plane ident. pin 1 1 8 16 9 detail e j j1 b c d a k k1 h g detail e f m l 2x l/2 u s u 0.15 (0.006) t s u 0.15 (0.006) t s u m 0.10 (0.004) v s t 0.10 (0.004) t v w 0.25 (0.010) 16x ref k n n
mc74vhc157 http://onsemi.com 7 package dimensions soic eiaj16 m suffix case 96601 issue o h e a 1 dim min max min max inches --- 2.05 --- 0.081 millimeters 0.05 0.20 0.002 0.008 0.35 0.50 0.014 0.020 0.18 0.27 0.007 0.011 9.90 10.50 0.390 0.413 5.10 5.45 0.201 0.215 1.27 bsc 0.050 bsc 7.40 8.20 0.291 0.323 0.50 0.85 0.020 0.033 1.10 1.50 0.043 0.059 0 0.70 0.90 0.028 0.035 --- 0.78 --- 0.031 a 1 h e q 1 l e 10 0 10 l e q 1 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions d and e do not include mold flash or protrusions and are measured at the parting line. mold flash or protrusions shall not exceed 0.15 (0.006) per side. 4. terminal numbers are shown for reference only. 5. the lead width dimension (b) does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the lead width dimension at maximum material condition. dambar cannot be located on the lower radius or the foot. minimum space between protrusions and adjacent lead to be 0.46 ( 0.018). m l detail p view p c a b e m 0.13 (0.005) 0.10 (0.004) 1 16 9 8 d z e a b c d e e l m z
mc74vhc157 http://onsemi.com 8 on semiconductor and are trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scill c data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthori zed use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. publication ordering information central/south america: spanish phone : 3033087143 (monfri 8:00am to 5:00pm mst) email : onlitspanish@hibbertco.com tollfree from mexico: dial 018002882872 for access then dial 8662979322 asia/pacific : ldc for on semiconductor asia support phone : 13036752121 (tuefri 9:00am to 1:00pm, hong kong time) toll free from hong kong & singapore: 00180044223781 email : onlitasia@hibbertco.com japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. mc74vhc157/d north america literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com fax response line: 3036752167 or 8003443810 toll free usa/canada n. american technical support : 8002829855 toll free usa/canada europe: ldc for on semiconductor european support german phone : (+1) 3033087140 (monfri 2:30pm to 7:00pm cet) email : onlitgerman@hibbertco.com french phone : (+1) 3033087141 (monfri 2:00pm to 7:00pm cet) email : onlitfrench@hibbertco.com english phone : (+1) 3033087142 (monfri 12:00pm to 5:00pm gmt) email : onlit@hibbertco.com european tollfree access*: 0080044223781 *available from germany, france, italy, uk, ireland
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